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200PIN DDR2 533 SO-DIMM

512MB With 64Mx8 CL4

Transcend Information Inc.

Timing Parameters & Specifications

(These AC characteristics were tested on the Component)

Parameter Symbol Min Max Unit Note

DQ output access time from CK & /CK

tAC

-500 +500

DQS output access time from CK & /CK tDQSCK -450 +450 ps

CK high-level width

tCH 0.45

0.55 tCK

CK low-level width tCL 0.45 0.55 tCK

CK half period

tHP

min(tCL,tCH) X

Clock cycle time, CL=x

tCK

3750 8000 ps

DQ and DM input hold time

tDH

225 x

DQ and DM input setup time

tDS 100 X ps

Control & Address input pulse width for each input

tIPW 0.6 x tCK

DQ and DM input pulse width for each input

tDIPW 0.35 X

tCK

Data-out high-impedance time from CK/CK

tHZ X

tAC max

DQS low-impedance time from CK/CK

tLZ(DQS) tAC min

tAC max ps

DQ low-impedance time from CK/CK

tLZ(DQ) 2*tAC min

TAC max

DQS-DQ skew for DQS and associated DQ signals

tDQSQ

X 300 ps

DQ hold skew factor

tQHS

X 400

DQ/DQS output hold time from DQS

tQH

tHP - tQHS X ps

Write command to first DQS latching transition

tDQSS WL-0.25 WL+0.25 tCK

DQS input high pulse width

tDQSH 0.35 X tCK

DQS input low pulse width

tDQSL 0.35 X tCK

DQS falling edge to CK setup time

tDSS

0.2 X

tCK

DQS falling edge hold time from CK

tDSH 0.2

X tCK

Mode register set command cycle time

tMRD 2 X tCK

Write postamble

tWPST

0.4 0.6 tCK

Write preamble

tWPRE

0.35 X tCK

Address and control input hold time

tIH

375 X

Address and control input setup time

tIS 250 X ps

Read preamble

tRPRE 0.9 1.1 tCK

Read postamble

tRPST 0.4 0.6 tCK

Active to active command period for 1KB page size

products

tRRD 7.5 X

Active to active command period for 2KB page size

products

tRRD 10

X ns

Four Activate Window for 1KB page size products

tFAW 37.5

Four Activate Window for 2KB page size products

tFAW

50 ns

1 2 3 4 5 6 7 8 9 10 11

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Transcend TS64MSQ64V5J Scheda Tecnica Pagina 8

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